Publications

1. Articles publiés dans des revues avec comité de lecture

[1] H. Mahvash Mohammadi, Y. Savaria and J.M.P. Langlois, “A Hybrid Deinterlacing Algorithm Exploiting Reverse Motion Estimation,” IET Image Processing, accepté, Jan. 2011.

[2] G.-A. Bilodeau, A. Torabi, M. Lévesque, C. Ouellet, J.M. P. Langlois, P. Lema and L. Carmant “Body temperature estimation of a moving subject from thermographic images,” Machine Vision and Applications, online Jan 2011, http://www.springerlink.com/content/a56464521h522911/.

[3] S. Gao, N. Chabini, D. Al-Khalili and J.M.P. Langlois, “FPGA-based efficient design approaches for large-size two’s complement squarers,” The Journal of Signal Processing Systems, vol. 58, No. 1, January 2010, pp. 3-15.

[4] A. Islam, U. Iqbal, J.M.P. Langlois and A. Noureldin, “Implementation methodology of embedded land vehicle positioning using an integrated GPS and multi-sensor system,” Integrated Computer-Aided Engineering, vol. 17, No. 1, January 2010, pp. 69-83.

[5] M. Lévesque, J.M.P. Langlois, P. Lema, R. Courtemanche, G.-A. Bilodeau and L. Carmant, “Synchronized gamma oscillations (30-50 Hz) in the amygdalo-hippocampal network in relation with seizure propagation and severity,” Neurobiology of disease, Vol. 35, No. 2, August 2009, pp. 209-218.

[6] H. Mahvash Mohammadi, J.M.P. Langlois and Y. Savaria, “A five-field motion compensated deinterlacing method based on vertical motion,” IEEE Transactions on Consumer Electronics, August 2007, pp. 1117-1124.

[7] S. Gao, N. Chabini, D. Al-Khalili and J.M.P. Langlois, “Optimized realizations of large integer multipliers and squarers using embedded blocks,” IET Computers & Digital Techniques, vol. 1, issue 1, January 2007, pp. 9-16.

[8] J.M.P. Langlois and D. Al-Khalili, “Carry-free approximate squaring functions with O(n) complexity and O(1) delay,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 5, May 2006, pp. 374-378.

[9] J.M.P. Langlois and D. Al-Khalili, “Phase to Sinusoid Amplitude Conversion Techniques for Direct Digital Frequency Synthesis,” IEE Proceedings on Circuits, Devices and Systems, vol. 151, no. 6, De-cember 2004, pp. 519-528.

[10] J.M.P. Langlois and D. Al-Khalili, “Novel approach to the design of direct digital frequency syn-thesizers based on linear interpolation,” IEEE Transactions on Circuits and Systems II: Analog and Dig-ital Signal Processing, vol. 50, no. 9, September 2003, pp. 567-578.

[11] J.M.P. Langlois, D. Al-Khalili, and R.J. Inkol, “Polyphase filter approach for high performance, FPGA-based quadrature demodulation,” The Journal of VLSI Signal Processing Systems, vol. 32, no.3, November 2002, pp. 237-254.

2. Autres contributions avec comité de lecture

[12] G.-A. Bilodeau, R. Ghali, S. Desgents, R. Farah, P.-L. St-Onge, S. Duss, J.M. P. Langlois and L. Carmant “Where is the rat? Tracking in low contrast thermographic images,” Proceedings of the IEEE Workshop on Object Tracking and Classification Beyond the Visible Spectrum, June 2011.

[13] S. Rajotte, D.C. Gil and J.M.P. Langlois, “Combining ISA extensions and subsetting for improved ASIP performance and cost,” Proceedings of IEEE International Conference on Circuits and Systems, May 2011.

[14] D.C. Gil, R. Farah, J.M.P. Langlois, G.-A. Bilodeau and Y. Savaria, “Image contrast enhancement for surveillance applications,” Proceedings of IEEE International Conference on Circuits and Systems, May 2011.

[15] F.C.J. Allaire, J.M.P. Langlois, G. Labonté and M. Tarbouchi, “Two-tiered resolution real-time path evaluation”, Proceedings of International Conference on Evolutionary Computation, October 2010.

[16] P. Aubertin, H. Mahvash Mohammadi, Y. Savaria and J.M.P. Langlois, “A high performance ASIP implementation of PBDI – a new intra-field deinterlacing method,” Proceedings of IEEE NEWCAS, June 2009.

[17] A. Islam, J.M.P. Langlois and A. Noureldin, “A design methodology for the implementation of embedded vehicle navigation systems,” Proceedings of IEEE EIT, June 2009.

[18] G.-A. Bilodeau, M. Lévesque, J.M.P. Langlois, P. Lema and L. Carmant, “Thermographic body temperature measurement using a mean-shift tracker,” Proceedings of the International Conference on Bio-inspired Systems and Signal Processing, January 2009.

[19] A. Torabi, G.-A. Bilodeau, M. Lévesque, J.M.P. Langlois, P. Lema and L. Carmant, “Measuring animal body temperature in thermographic video using particle filter tracking,” Lecture Notes in Com-puter Science: Advances in Visual Computing, Vol. 5358, 2008, pp. 1081-1091.

[20] S. Fontaine, S. Goyette, J.M. Pierre Langlois and G. Bois, “Acceleration of a target tracking algo-rithm using an application specific instruction set processor,” Proceedings of the IEEE International Conference on Computer Design, October 2008.

[21] M.-A. Daigneault, J.M. Pierre Langlois and J.-P. David, “Application specific instruction set pro-cessor specialized for block motion estimation,” Proceedings of the IEEE International Conference on Computer Design, October 2008.

[22] M. Lévesque, P. Lema, J.M.P. Langlois, R. Courtemanche and L. Carmant, “Local field potential synchrony in the amygdalo-hippocampal network during kainate induced-seizures,” 62nd Annual Meet-ing of the Eastern Association of Electroencephalographers, Clinical Neurophysiology, vol. 119, Sep-tember 2008, p. e96.

[23] S. Tchoulack, J.M.P. Langlois and F. Cheriet, “Real-time detection and correction of specular ref-lexions in endoscopic video,” Proceedings of IEEE NEWCAS-TAISA, June 2008.

[24] G.A. Bouyela, J.M.P. Langlois and Y. Savaria, “Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing,” Proceedings of IEEE NEWCAS-TAISA, June 2008, pp. 37-40.

[25] M.Y. Kong, J.M.P. Langlois and D. Al-Khalili, “Efficient FPGA implementation of complex mul-tipliers using the logarithmic number system,” Proceedings of the IEEE International Symposium on Circuits and Systems, May 2008.

[26] N. Hireche, J.M.P. Langlois and G. Nicolescu, “A systolic array for sequence comparison based on two Logic levels processing element,” Proceedings of the joint IEEE Mid-West Symposium and North-East Workshop on Circuits and Systems, August 2007.

[27] S. Gao, N. Chabini, D. Al-Khalili and J.M.P. Langlois, “FPGA-based efficient design approach for large-size two’s complement squarers,” Proceedings of the IEEE International Conference on Applica-tion-specific Systems, Architectures and Processors, July 2007.

[28] H. Mahvash Mohammadi, J.M.P. Langlois and Y. Savaria, “A Threshold-based de-interlacing algorithm using motion compensation and directional interpolation,” Proceedings of the IEEE Interna-tional Conference on Electronics, Circuits and Systems, December 2006.

[29] S. Gao, N. Chabini, D. Al-Khalili and J.M.P. Langlois, “Efficient FPGA-based realization of com-plex squarer and complex conjugate using embedded multipliers,” Proceedings of the IEEE International SOC Conference, September 2006, pp. 21-24.

[30] H. Mahvash Mohammadi, Y. Savaria and J.M.P. Langlois, “Real-time ELA de-interlacing with the Xtensa reconfigurable processor,” Proceedings of IEEE NEWCAS, June 2006, pp. 25-28.

[31] S. Gao, N. Chabini, D. Al-Khalili and J.M.P. Langlois, “Efficient realization of large integers mul-tipliers and squarers,” Proceedings of IEEE NEWCAS, June 2006, pp. 37-40.

[32] J.M.P. Langlois, “Design and implementation of high sampling rate programmable FIR filters in FPGAs,” Proceedings of IEEE NEWCAS, June 2006, pp. 237-240.

[33] N. Hireche, J.M.P. Langlois and G. Nicolescu, “A review of hardware architectures for bioinfor-matics algorithm acceleration,” Proceedings of the IEEE Canadian Conference on Electrical and Com-puter Engineering, May 2006, pp. 1926-1929.

[34] S. Gao, N. Chabini, D. Al-Khalili and J.M.P. Langlois, “An optimized design approach for squaring large integers using embedded hardwired multipliers,” Proceedings of the ACS/IEEE International Conference on Computer Systems and Applications, March 2006, pp. 248-254.

[35] S. Gao, N. Chabini, D. Al-Khalili and J.M.P. Langlois, “Optimized multipliers for large unsigned integers,” Proceedings of the NORCHIP Conference, November 2005, pp. 78-81.

[36] G. Gilbert and J.M.P. Langlois, “Multipath greedy algorithm for canonical representation of num-bers in the double base number system,” Proc. of IEEE NEWCAS, Québec, QC, June 2005, pp. 39-42.

[37] J.M.P. Langlois, D. Al-Khalili and H. Al-Hertani, “Carry free, bit parallel approximate squarers with linear complexity and constant delay,” Proceedings of IEEE NEWCAS, June 2004, pp. 385-388.

[38] J.M.P. Langlois, “Design of Linear Phase FIR Filters using Particle Swarm Optimization,” Pro-ceedings of the Queen’s Biennial Symposium on Communications, May 2004, pp. 172-174.

[39] J.M.P. Langlois and D. Al-Khalili, “Low power direct digital frequency synthesizers in 0.18 ?m CMOS,” Proceedings of the IEEE Custom Integrated Circuits Conference, September 2003, pp. 283-286.

[40] J.M.P. Langlois and D. Al-Khalili, “Piecewise continuous linear interpolation of the sine function for direct digital frequency synthesis,” Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, PA, June 2003, pp. 579-582.

[41] Q. Liu, J.M.P. Langlois, D. Al-Khalili, V. Szwarc and R. Inkol, “Synthesis of a 12-bit complex mixer for FPGA implementation,” Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, Montréal, QC, May 2003.

[42] J.M.P. Langlois and D. Al-Khalili, “A quadrature direct digital frequency synthesizer architecture using piecewise-continuous linear segments,” Proceedings of the Queen’s Biennial Symposium on Communications, Kingston, Ontario, June 2002, pp. 463-467.

[43] J.M.P. Langlois and D. Al-Khalili, “A new approach to the design of low power direct digital fre-quency synthesizers,” Proceedings of the IEEE International Frequency Control Symposium, New Or-leans, Louisiana, May 2002.

[44] J.M.P. Langlois and D. Al-Khalili, “Hardware optimized direct digital frequency synthesizer archi-tecture with 60 dBc spectral purity,” Proceedings of the IEEE International Symposium on Circuits and Systems, Phoenix, Arizona, May 2002, pp. 361-364.

[45] J.M.P. Langlois and D. Al-Khalili, “A low power direct digital frequency synthesizer with 60 dBc spectral purity,” Proceedings of the ACM Great Lakes Symposium on VLSI, April 2002, pp. 166-171.

[46] J.M.P. Langlois and D. Al-Khalili, “Efficient sine amplitude computation for direct digital frequen-cy synthesis,” Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, Cairo, Egypt, December 2001.

[47] J.M.P. Langlois and D. Al-Khalili, “ROM size reduction with low processing cost for direct digital frequency synthesis,” Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria BC, 26-28 Aug. 2001.

[48] J.M.P. Langlois, D. Al-Khalili, and R.J. Inkol, “Polyphase filter approach for high performance, FPGA-based quadrature demodulation” in Proceedings of DSP-Deutschland, Munich, 11-12 October 2000, pp. 243-250.

[49] J.M.P. Langlois, D. Al-Khalili, and R.J. Inkol, “A high performance, wide bandwidth, low cost FPGA-based quadrature demodulator”, in Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton AB, 9-12 May 1999, pp. 497-502.

3. Contributions sans comité de lecture

[50] D.C. Gil, R. Farah, J.M.P. Langlois, G.-A. Bilodeau et Y. Savaria, “Analyse comparative d’algorithmes d’amélioration du contraste pour des images de surveillance,” présenté au 79e congrès de l’ACFAS, Sherbrooke, 2011.

[51] S. Rajotte, D.C. Gil et J.M.P. Langlois, “Amélioration de la performance et du coût d’un ASIP en combinant l’extension et la réduction du jeu d’instructions,” présenté au 79e congrès de l’ACFAS, Sher-brooke, 2011.

[52] C. P. Arasanz, M. Lévesque, J. Bourget-murray, J.M.P. Langlois and R. Courtemanche, “Multi-site interactions between rodent cerebellar cortex slow oscillations and with free whisking,” présenté à So-ciety for Neuroscience Annual Meeting, San Diego, Nov. 2010.

[53] R. Farah, J.M.P. Langlois and G.A. Bilodeau, “Une méthode pour déterminer la posture d’un rat à l’aide d’un système de vision numérique,” présenté au 78e congrès de l’ACFAS, Montréal, 2010.

[54] Q. Gan, J.M.P. Langlois and Y. Savaria, “Challenges to the implementation of particle filters in application-specific instruction-set processors,” présenté au 78e congrès de l’ACFAS, Montréal, 2010.

[55] J.M.P. Langlois, “A low power direct digital frequency synthesizer with 60 dBc spectral purity rea-lized in 0.18?m CMOS,” présenté au Symposium on Microelectronics Research & Development In Canada (MR&DCAN 2002), Ottawa, Ontario, June 2002.

[56] J.M.P. Langlois, D. Al-Khalili and R.J. Inkol, “A conceptual framework for high performance FPGA-based digital quadrature demodulation,” présenté au Technical Cooperation Program, Electronic Warfare Systems, Technical Panel 4, Ottawa, Ontario, September 2001.

4. Contributions à des applications concrètes

[57] J.M.P. Langlois and D. Al-Khalili, "Phase to sine amplitude conversion system and method," U.S. patent 6,657,573, 2 December 2003.

5. Thèses

[58] J.M.P. Langlois, "Novel design approach and architectures for sinusoid output direct digital frequency synthesis," Ph.D. thesis, Royal Military College of Canada, 2002.

[59] J.M.P. Langlois, "Design and implementation of wide-band quadrature demodulators on Field Programmable Gate Arrays", Master's thesis, Royal Military College of Canada, 1999.